{"id":5664,"date":"2016-05-16T14:58:30","date_gmt":"2016-05-16T14:58:30","guid":{"rendered":"http:\/\/www.telecomstalk.com\/?p=5664"},"modified":"2018-06-06T09:59:12","modified_gmt":"2018-06-06T09:59:12","slug":"ultrasoc-announces-significant-product-update-improved-support-analytics-cpu-capability","status":"publish","type":"post","link":"https:\/\/www.telecomstalk.com\/?p=5664","title":{"rendered":"UltraSoC Announces Significant Product Update, Improved Support for Analytics and \u2018any CPU\u2019 Capability"},"content":{"rendered":"<p>UltraSoC today announced the latest version of its advanced semiconductor IP and software tools for SoC development, debug, optimization and hardware security. The latest release in UltraSoC\u2019s continuous development program includes extended support for data analytics and visualization, improved performance monitoring and system optimization capabilities, enhanced integration with third-party tool-chains, improved support for functional safety applications, and General Availability (GA) of new analytics and communications IP.<\/p>\n<p>As the cost of developing complex SoCs continues to rise, and the business risks from schedule slippage become larger, the industry has realized that better tools for debug, verification and optimization are critical. The advent of emulation and prototyping platforms has eased pre-silicon tasks, but post-silicon verification and optimization remains a major challenge for the industry. UltraSoC addresses this challenge.<\/p>\n<p>Many of the new capabilities and features are in software and tools \u2013 particularly in interfacing and supporting standard development environments. Specifically:<\/p>\n<p>\u2022         Richer support for analytics and visualization, leading to the use of \u201cBig Data\u201d techniques for debugging and development<br \/>\n\u2022         New tools and analysis capabilities to assist in performance monitoring and system optimization<br \/>\n\u2022         Enhanced support for developers using Python scripts to interact with UltraSoC IP for post-processing, analytics and visualization<br \/>\n\u2022         Migration to Eclipse version 4.5 (\u201cMars\u201d) with all the capabilities that come from an industry standard IDE<br \/>\n\u2022         Support for the GDB industry standard open-source debugger<br \/>\n\u2022         Direct integration with Lauterbach\u2019s industry standard TRACE32 development environment<br \/>\n\u2022         Direct integration with the new version of CEVA\u2019s toolchain for CEVA DSP<\/p>\n<p>New hardware and semiconductor IP capabilities include:<\/p>\n<p>\u2022         Enhanced Processor Analytic Modules to interface to MIPS and CEVA cores for debugging, trace and run-control. These complement the existing ARM and Xtensa core support<br \/>\n\u2022         Capability to support other cores, including the open-source RISC V core<br \/>\n\u2022         Support for ECC, parity and check sum logic, important for high-reliability systems. This is a key part of UltraSoC\u2019s capabilities to support functional safety, automotive and ISO26262<br \/>\n\u2022         General availability of the new Universal Streaming Communicator (USC) that enables a variety of interface and communication systems to the SoC, including serial wire debug style communication and a high speed SerDes interface<\/p>\n<p>\u201cUltraSoC is committed to an aggressive program of continuous development for our products,\u201d said Rupert Baines, UltraSoC CEO. \u201cOur technology helps SoC developers to understand how their chip really operates post-silicon: simplifying software development, accelerating time-to-market, fixing bugs and optimizing performance. The new capabilities we are announcing today, engineered in response to extensive customer feedback and experience in the field, represent another step forward in the paradigm shift we are enabling in SoC design; improved analytics and visualization; addressing a far wider range of hardware applications; and giving SoC teams complete freedom in their choice of development flow and tools.\u201d<\/p>\n<p>UltraSoC\u2019s suite of silicon IP allows designers to create an on-chip infrastructure that non-intrusively monitors the digital aspects of the chip\u2019s behavior \u2013 both hardware and software. The engineering team can gain a much more intimate understanding of the often complex interactions between diverse on-chip processor blocks, custom logic, and system software. These capabilities are valuable both in development and in-field, when they can be used to spot unexpected behavior caused by bugs or by malicious interference, and to analyze performance trends.<\/p>\n<p>UltraSoC was recently named by Gartner Inc as one of its \u201cCool Vendors\u201d in the Embedded Software and Systems market; and recognized by Mishcon de Reya and City AM in its Leap 100 list of the UK\u2019s most exciting, fast-growth companies. Last fall the company was named Best New Company at the 2015 Elektra Awards.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>UltraSoC today announced the latest version of its advanced semiconductor IP and software tools for SoC development, debug, optimization and hardware security. The latest release in UltraSoC\u2019s continuous development program includes extended support for data analytics and visualization, improved performance &#8230; <span class=\"more-link\"><a href=\"https:\/\/www.telecomstalk.com\/?p=5664\" class=\"more-link\">Read More<\/a><\/span><\/p>\n","protected":false},"author":4,"featured_media":0,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[1919,1838,1835],"class_list":["post-5664","post","type-post","status-publish","format-standard","hentry","tag-gartner-inc","tag-rupert-baines","tag-ultrasoc"],"_links":{"self":[{"href":"https:\/\/www.telecomstalk.com\/index.php?rest_route=\/wp\/v2\/posts\/5664","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.telecomstalk.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.telecomstalk.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.telecomstalk.com\/index.php?rest_route=\/wp\/v2\/users\/4"}],"replies":[{"embeddable":true,"href":"https:\/\/www.telecomstalk.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=5664"}],"version-history":[{"count":2,"href":"https:\/\/www.telecomstalk.com\/index.php?rest_route=\/wp\/v2\/posts\/5664\/revisions"}],"predecessor-version":[{"id":5666,"href":"https:\/\/www.telecomstalk.com\/index.php?rest_route=\/wp\/v2\/posts\/5664\/revisions\/5666"}],"wp:attachment":[{"href":"https:\/\/www.telecomstalk.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=5664"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.telecomstalk.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=5664"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.telecomstalk.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=5664"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}